Invention Grant
- Patent Title: Methods of forming integrated circuit package
- Patent Title (中): 集成电路封装形成方法
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Application No.: US14298711Application Date: 2014-06-06
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Publication No.: US09281254B2Publication Date: 2016-03-08
- Inventor: Chen-Hua Yu , Chi-Hsi Wu , Wen-Chih Chiou , Hsiang-Fan Lee , Shih-Peng Tai , Tang-Jung Chiu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L21/66 ; H01L21/78 ; H01L23/00

Abstract:
A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.
Public/Granted literature
- US20150228550A1 Integrated Circuit Package and Methods of Forming Same Public/Granted day:2015-08-13
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