Invention Grant
- Patent Title: System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof
- Patent Title (中): 具有垂直互连的引线元件的系统级封装及其制造方法
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Application No.: US14310992Application Date: 2014-06-20
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Publication No.: US09281284B2Publication Date: 2016-03-08
- Inventor: Weng F. Yap , Zhiwei Gong
- Applicant: Weng F. Yap , Zhiwei Gong
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR INC.
- Current Assignee: FREESCALE SEMICONDUCTOR INC.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L23/66 ; H01L21/768 ; H01L23/31 ; H01L23/538 ; H01L23/00 ; H01L21/52 ; H01L23/552

Abstract:
System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.
Public/Granted literature
Information query
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