Invention Grant
- Patent Title: Single layer low cost wafer level packaging for SFF SiP
- Patent Title (中): 用于SFF SiP的单层低成本晶圆级封装
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Application No.: US13532119Application Date: 2012-06-25
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Publication No.: US09281292B2Publication Date: 2016-03-08
- Inventor: Chuan Hu , Vijay Nair
- Applicant: Chuan Hu , Vijay Nair
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/00 ; H01L25/03 ; H01L25/16 ; H01L21/56

Abstract:
In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.
Public/Granted literature
- US20130343022A1 SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP Public/Granted day:2013-12-26
Information query
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