Invention Grant
- Patent Title: Vertical cell-type semiconductor device having protective pattern
- Patent Title (中): 具有保护图案的垂直单元型半导体器件
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Application No.: US14151288Application Date: 2014-01-09
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Publication No.: US09281414B2Publication Date: 2016-03-08
- Inventor: Jin-Yeon Won , Joon-Hee Lee , Seung-Woo Paek , Dong-Seog Eun
- Applicant: Jin-Yeon Won , Joon-Hee Lee , Seung-Woo Paek , Dong-Seog Eun
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2013-0029103 20130319
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L27/115 ; H01L29/66

Abstract:
According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
Public/Granted literature
- US20140284695A1 VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE PATTERN Public/Granted day:2014-09-25
Information query
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