A variable resistance memory according to an embodiment includes: a first wiring; a second wiring provided above the first wiring and intersecting with the first wiring; a third wiring provided above the second wiring and intersecting with the second wiring; a first variable resistance element provided in an intersection region between the first wiring and the second wiring, the first variable resistance element including a first variable resistance layer formed on the first wiring, and an ion source electrode provided on the first variable resistance layer and penetrating through the second wiring, the ion source electrode being connected to the second wiring and including metal atoms; and a second variable resistance element provided in an intersection region between the second wiring and the third wiring, the second variable resistance element including a second variable resistance layer formed on the ion source electrode.