Invention Grant
- Patent Title: Method for forming pattern and method for manufacturing semiconductor device
- Patent Title (中): 形成图案的方法和制造半导体器件的方法
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Application No.: US14637558Application Date: 2015-03-04
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Publication No.: US09281480B2Publication Date: 2016-03-08
- Inventor: Yuriko Seino , Naoko Kihara
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Nixon & Vanderhye, P.C.
- Priority: JP2014-059140 20140320
- Main IPC: H01L51/00
- IPC: H01L51/00

Abstract:
In one embodiment, a method for forming pattern includes forming a guide layer on a substrate, forming a copolymer layer of a high-molecular block copolymer on the guide layer; and forming a phase-separation structure with a phase-separation cycle d by self-assembling the copolymer layer. The high-molecular block copolymer includes a first and a second polymer. The guide layer includes a first and a second region disposed on the substrate. Widths of the first and second region respectively are approximately (d/2)×n and (d/2)×m. Both of the first and second region are to be pinned with none of the first and second polymer. Surface energies of the first and second region are different from one another. Integers n and m are odd numbers. Value d is a phase-separation cycle of the high-molecular block copolymer.
Public/Granted literature
- US20150311442A1 METHOD FOR FORMING PATTERN AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2015-10-29
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