Invention Grant
US09281804B2 Semiconductor device with amplification circuit and output buffer circuit coupled to terminal
有权
半导体器件具有放大电路和输出缓冲电路耦合到端子
- Patent Title: Semiconductor device with amplification circuit and output buffer circuit coupled to terminal
- Patent Title (中): 半导体器件具有放大电路和输出缓冲电路耦合到端子
-
Application No.: US14024619Application Date: 2013-09-11
-
Publication No.: US09281804B2Publication Date: 2016-03-08
- Inventor: Masaru Iwabuchi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2012-200474 20120912
- Main IPC: H03K3/01
- IPC: H03K3/01 ; H03K3/011 ; H03K19/00 ; H03K19/003

Abstract:
The present invention is directed to solve a problem that, in a semiconductor device capable of generating a clock signal by coupling a quartz oscillator to an external terminal to which an I/O port is coupled, leak current of the I/O port which is in the inactive state disturbs activation of a clock. The semiconductor device has a first terminal, an amplification circuit coupled to the first terminal, and an output buffer whose output terminal is coupled to the first terminal. The output buffer has first and second transistors of a first conduction type coupled in series via a first node between a first power supply line and an output terminal, and the conduction states of the first and second transistors of the first conduction state are controlled in response to a first control signal which is applied commonly to the gate of each of the first and second transistors.
Public/Granted literature
- US09160311B2 Semiconductor device with amplification circuit and output buffer circuit coupled to terminal Public/Granted day:2015-10-13
Information query