Invention Grant
US09293560B2 Vertical nanowire transistor with axially engineered semiconductor and gate metallization
有权
具有轴向设计的半导体和栅极金属化的垂直纳米线晶体管
- Patent Title: Vertical nanowire transistor with axially engineered semiconductor and gate metallization
- Patent Title (中): 具有轴向设计的半导体和栅极金属化的垂直纳米线晶体管
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Application No.: US14534088Application Date: 2014-11-05
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Publication No.: US09293560B2Publication Date: 2016-03-22
- Inventor: Brian S. Doyle , Roza Kotlyar , Uday Shah , Charles C. Kuo
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; B82Y10/00 ; H01L29/423 ; H01L29/775 ; H01L29/06 ; H01L21/02 ; H01L29/16

Abstract:
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
Public/Granted literature
- US20150072490A1 VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION Public/Granted day:2015-03-12
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