Invention Grant
US09299577B2 Methods for etching a dielectric barrier layer in a dual damascene structure
有权
用于蚀刻双镶嵌结构中的电介质阻挡层的方法
- Patent Title: Methods for etching a dielectric barrier layer in a dual damascene structure
- Patent Title (中): 用于蚀刻双镶嵌结构中的电介质阻挡层的方法
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Application No.: US14540577Application Date: 2014-11-13
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Publication No.: US09299577B2Publication Date: 2016-03-29
- Inventor: He Ren , Chia-Ling Kao , Sean Kang , Jeremiah T P Pender , Srinivas D. Nemani , Mehul B. Naik
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/768 ; H01L21/311 ; H01L21/02 ; H01L21/033 ; H01L21/3065 ; H01L21/306
Abstract:
Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.
Public/Granted literature
- US20150214101A1 METHODS FOR ETCHING A DIELECTRIC BARRIER LAYER IN A DUAL DAMASCENE STRUCTURE Public/Granted day:2015-07-30
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