Invention Grant
- Patent Title: Semiconductor package and manufacturing method therefor
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US13326502Application Date: 2011-12-15
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Publication No.: US09299678B2Publication Date: 2016-03-29
- Inventor: Masahiro Kyozuka , Toru Hizume , Akihiko Tateiwa
- Applicant: Masahiro Kyozuka , Toru Hizume , Akihiko Tateiwa
- Applicant Address: JP Nagano-Shi
- Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Current Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Current Assignee Address: JP Nagano-Shi
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2010-280951 20101216
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/00 ; H01L23/31 ; H01L25/065 ; H05K1/18 ; H01L21/683 ; H01L25/00 ; H05K3/46
Abstract:
According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.
Public/Granted literature
- US20120153509A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR Public/Granted day:2012-06-21
Information query
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