Invention Grant
- Patent Title: Multi-gate and complementary varactors in FinFET process
- Patent Title (中): FinFET工艺中的多栅极和互补变容二极管
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Application No.: US13801089Application Date: 2013-03-13
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Publication No.: US09299699B2Publication Date: 2016-03-29
- Inventor: Chi-Hsien Lin , Ying-Ta Lu , Hsien-Yuan Liao , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L27/08
Abstract:
A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.
Public/Granted literature
- US20140264628A1 Multi-Gate and Complementary Varactors in FinFET Process Public/Granted day:2014-09-18
Information query
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