Invention Grant
US09299832B2 High voltage lateral DMOS transistor with optimized source-side blocking capability
有权
高电压横向DMOS晶体管，具有优化的源极侧阻断能力
- Patent Title: High voltage lateral DMOS transistor with optimized source-side blocking capability
- Patent Title (中): 高电压横向DMOS晶体管，具有优化的源极侧阻断能力
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Application No.: US14567196Application Date: 2014-12-11
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Publication No.: US09299832B2Publication Date: 2016-03-29
- Inventor: Philip Leland Hower , Sameer Pendharkar , Marie Denison
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Tuenlap D. Chan; Frank D. Cimino
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/336 ; H01L29/78 ; H01L29/08 ; H01L29/10 ; H01L29/06 ; H01L21/266 ; H01L21/225
Abstract:
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
Public/Granted literature
- US20150171212A1 HIGH VOLTAGE LATERAL DMOS TRANSISTOR WITH OPTIMIZED SOURCE-SIDE BLOCKING CAPABILITY Public/Granted day:2015-06-18
Information query
IPC分类:
