Invention Grant
- Patent Title: Apparatus of three-dimensional integrated-circuit chip using fault-tolerant test through-silicon-via
- Patent Title (中): 三维集成电路芯片的装置采用容错测试，通过硅通孔
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Application No.: US14210718Application Date: 2014-03-14
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Publication No.: US09304167B2Publication Date: 2016-04-05
- Inventor: Ting-Ting Hwang , Fu-Wei Chen
- Applicant: National Tsing Hua University
- Applicant Address: TW Hsinchu
- Assignee: NATIONAL TSING HUA UNIVERSITY
- Current Assignee: NATIONAL TSING HUA UNIVERSITY
- Current Assignee Address: TW Hsinchu
- Agency: Jackson IPG PLLC
- Agent Demian K. Jackson
- Priority: TW102148566A 20131226
- Main IPC: H03K19/00
- IPC: H03K19/00 ; G01R31/3185
Abstract:
An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.
Public/Granted literature
- US20150185274A1 Apparatus of Three-Dimensional Integrated-Circuit Chip Using Fault-Tolerant Test Through-Silicon-Via Public/Granted day:2015-07-02
Information query
