A receiver circuit includes a deserialization unit, a sampling clock control unit and a sampling clock generation unit. The deserialization unit is configured to receive sampling clock signals, sample a plurality of input data signals, and generate a plurality of internal data signals. The sampling clock control unit is configured to generate a delay control signal and a synchronization completion signal in response to the plurality of internal data signals and a first group of clock signals. The sampling clock generation unit delays the first group of clock signals and provides the delayed first group of clock signals as the sampling clock signals in response to the delay control signal, and provides a second group of clock signals having a phase leading by a predetermined amount with respect to the first group of clock signals, as the sampling clock signals in response to the synchronization completion signal.