Invention Grant
US09304790B2 Masking power usage of co-processors on field-programmable gate arrays using negative feedback to adjust a voltage variation on an FPGA power distribution trace
有权
使用负反馈来掩蔽现场可编程门阵列上的协处理器的功率使用，以调整FPGA功率分布曲线上的电压变化
- Patent Title: Masking power usage of co-processors on field-programmable gate arrays using negative feedback to adjust a voltage variation on an FPGA power distribution trace
- Patent Title (中): 使用负反馈来掩蔽现场可编程门阵列上的协处理器的功率使用，以调整FPGA功率分布曲线上的电压变化
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Application No.: US13978877Application Date: 2013-01-31
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Publication No.: US09304790B2Publication Date: 2016-04-05
- Inventor: Kevin Fine , Ezekiel Kruglick
- Applicant: Empire Technology Development LLC
- Applicant Address: US DE Wilmington
- Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee Address: US DE Wilmington
- Agency: Turk IP Law, LLC
- International Application: PCT/US2013/024162 WO 20130131
- International Announcement: WO2014/120209 WO 20140807
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F11/30 ; G06F9/455 ; G06F21/00 ; G06F21/55
Abstract:
Technologies are generally described for masking power usage of co-processors on field-programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a held-programmable gate array (FPGA). The moat brick circuits may be configured to use negative feedback and/or noise to mask the power usage variations of the co-processor from other co-processors on the FPGA.
Public/Granted literature
- US20140237284A1 MASKING POWER USAGE OF CO-PROCESSORS ON FIELD-PROGRAMMABLE GATE ARRAYS Public/Granted day:2014-08-21
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