A processor system according to the present invention includes a storage unit (10), a control information area (12) that stores an access prohibit flag (13) capable of switching from an allow side to a prohibit side, a main PEa that issues an access request to the storage unit (10) and a request for rewriting a copy register (32), a security PE that evaluates whether or not the request for rewriting the copy register (32) is valid, the copy register (32) that stores, when the access prohibit flag (13) is set to the allow side, a value corresponding to the allowance and, when the access prohibit flag (13) is set to the prohibit side, a value corresponding to an evaluation result by the security PE, and an access control circuit (21) that controls whether or not to allow access from the main PEa to the storage unit (10) based on an output value from the copy register (32).