Invention Grant
US09305130B2 Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure
有权
用于形成半导体布局图案，半导体布局图案和半导体结构的方法
- Patent Title: Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure
- Patent Title (中): 用于形成半导体布局图案，半导体布局图案和半导体结构的方法
-
Application No.: US14445037Application Date: 2014-07-28
-
Publication No.: US09305130B2Publication Date: 2016-04-05
- Inventor: Jie Zhao , Huabiao Wu
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L29/66
- IPC: H01L29/66 ; G06F17/50 ; H01L29/78 ; H01L29/417
Abstract:
A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first layout patterns toward a direction opposite to the axial line to form at least a first shifted portion in each first layout pattern, and outputting the first layout patterns and the first shifted portions on a first mask.
Public/Granted literature
Information query
IPC分类:
