Provided is a semiconductor memory device and a method of erasing the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit unit configured to apply a pre-erase voltage, an erase voltage, and an erase operation voltage to the memory cell array so as to erase data stored in the plurality of memory cells when an erase operation is performed. The memory cell array includes a plurality of source selection transistors, the plurality of memory cells, and a plurality of drain selection transistors that are connected between a source line and a bit line. When the pre-erase voltage is applied to the source line during the erase operation, different erase operation voltages are applied to an outermost source selection transistor adjacent to the source line among the plurality of source selection transistor and the other selection transistors.