Invention Grant
US09305655B2 Solving MLC NAND paired page program using reduced spatial redundancy
有权
使用减少的空间冗余来解决MLC NAND配对页面程序
- Patent Title: Solving MLC NAND paired page program using reduced spatial redundancy
- Patent Title (中): 使用减少的空间冗余来解决MLC NAND配对页面程序
-
Application No.: US14038749Application Date: 2013-09-27
-
Publication No.: US09305655B2Publication Date: 2016-04-05
- Inventor: Lan Dinh Phan
- Applicant: Lan Dinh Phan , Virtium Technology, Inc.
- Applicant Address: US CA Rancho Santa Margarita
- Assignee: Virtium Technology, Inc.
- Current Assignee: Virtium Technology, Inc.
- Current Assignee Address: US CA Rancho Santa Margarita
- Main IPC: G11C14/00
- IPC: G11C14/00 ; G06F3/00 ; G11C16/22 ; G06F3/06 ; G11C11/56 ; G11C29/00
Abstract:
Reduced spatial redundancy of lower bits data provides data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory assists in restoring the data, using less than a full back up storage.
Public/Granted literature
- US20150092487A1 Solving MLC NAND paired page program using reduced spatial redundancy Public/Granted day:2015-04-02
Information query
