Invention Grant
- Patent Title: Method of manufacturing semiconductor integrated circuit device
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Application No.: US14738846Application Date: 2015-06-13
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Publication No.: US09305824B2Publication Date: 2016-04-05
- Inventor: Masaaki Shinohara , Satoshi Iida
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2014-135896 20140701
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/762 ; H01L29/66 ; H01L21/308

Abstract:
Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.
Public/Granted literature
- US20160005640A1 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2016-01-07
Information query
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