Invention Grant
- Patent Title: Method of forming stressed SOI layer
- Patent Title (中): 形成应力SOI层的方法
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Application No.: US14526005Application Date: 2014-10-28
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Publication No.: US09305828B2Publication Date: 2016-04-05
- Inventor: Denis Rideau , Emmanuel Josse , Olivier Nier
- Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Montrouge FR Crolles
- Assignee: STMicroelectronics SA,STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics SA,STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Montrouge FR Crolles
- Agency: Seed IP Law Group PLLC
- Priority: FR1360674 20131031
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/762 ; H01L21/02 ; H01L29/78 ; H01L21/84 ; H01L21/324

Abstract:
One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.
Public/Granted literature
- US20150118824A1 METHOD OF FORMING STRESSED SOI LAYER Public/Granted day:2015-04-30
Information query
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