Invention Grant
- Patent Title: 3D package with through substrate vias
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Application No.: US14528765Application Date: 2014-10-30
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Publication No.: US09305877B1Publication Date: 2016-04-05
- Inventor: Chen-Hua Yu , Mirng-Ji Lii , Hung-Yi Kuo , Hao-Yi Tsai , Chao-Wen Shih , Tsung-Yuan Yu , Min-Chien Hsiao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L23/522 ; H01L23/528 ; H01L23/31 ; H01L21/56

Abstract:
A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.
Information query
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