Invention Grant
- Patent Title: Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
- Patent Title (中): 用于交错堆叠半导体管芯的装置和相关方法
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Application No.: US14020549Application Date: 2013-09-06
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Publication No.: US09305905B2Publication Date: 2016-04-05
- Inventor: Trismardawi Tanadi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H03L7/00
- IPC: H03L7/00 ; H01L25/11 ; H01L25/10 ; G06F1/26
Abstract:
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.
Public/Granted literature
- US20150070056A1 APPARATUSES AND RELATED METHODS FOR STAGGERING POWER-UP OF A STACK OF SEMICONDUCTOR DIES Public/Granted day:2015-03-12
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