Invention Grant
- Patent Title: Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication
- Patent Title (中): 器件和具有封装表面导体和相邻沟槽的堆叠微电子封装及其制造方法
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Application No.: US14097459Application Date: 2013-12-05
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Publication No.: US09305911B2Publication Date: 2016-04-05
- Inventor: Michael B. Vincent , Jason R. Wright , Weng F. Yap
- Applicant: Michael B. Vincent , Jason R. Wright , Weng F. Yap
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Agent Sherry W. Schumm
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/02 ; H01L23/48 ; H01L21/00 ; H01L25/00 ; H01L23/00 ; H01L25/10

Abstract:
Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.
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