According to one embodiment, a memory includes a semiconductor layer including a trench which extends in a first direction, the trench having a first portion with a first depth and a second portion with a second depth deeper than the first depth, a gate insulating layer covering the semiconductor layer in the first portion, an element isolation layer covering the semiconductor layer in the second portion, the element isolation layer extending in a second direction from the second portion, a gate electrode provided on the gate insulating layer in the first portion and the element isolation layer in the second portion, the gate electrode filling the trench, and a third impurity region provided in the semiconductor layer directly below the second portion, the third impurity region being continuous in the first direction.