Invention Grant
- Patent Title: Power semiconductor transistor with improved gate charge
- Patent Title (中): 功率半导体晶体管具有改善的栅极电荷
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Application No.: US14220439Application Date: 2014-03-20
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Publication No.: US09306059B2Publication Date: 2016-04-05
- Inventor: Farshid Iravani , Jan Nilsson
- Applicant: KINETIC TECHNOLOGIES , SILICON FIDELITY
- Applicant Address: US CA Sunnyvale US CA Cupertino
- Assignee: Kinetic Technologies,Silicon Fidelity
- Current Assignee: Kinetic Technologies,Silicon Fidelity
- Current Assignee Address: US CA Sunnyvale US CA Cupertino
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L21/762 ; H01L29/06

Abstract:
A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.
Public/Granted literature
- US20150270389A1 POWER SEMICONDUCTOR TRANSISTOR WITH IMPROVED GATE CHARGE Public/Granted day:2015-09-24
Information query
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