Invention Grant
- Patent Title: Threshold gate and threshold logic array
- Patent Title (中): 阈值门限和阈值逻辑阵列
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Application No.: US13903490Application Date: 2013-05-28
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Publication No.: US09306151B2Publication Date: 2016-04-05
- Inventor: Sarma Vrudhula , Nishant S. Nukala , Niranjan Kulkarni
- Applicant: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
- Applicant Address: US AZ Scottsdale
- Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
- Current Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
- Current Assignee Address: US AZ Scottsdale
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: G11C11/15
- IPC: G11C11/15 ; H01L43/02 ; H03K19/18 ; H03K19/23 ; H03K19/20
Abstract:
Threshold gates and related circuitry are disclosed. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the threshold realization element is configured to switch the magnetic tunnel junction element from the first resistive state to the second resistive state in accordance with the threshold function. In this manner, the threshold gate may implement a threshold function that provides an output just like a complex Boolean function requiring several Boolean gates.
Public/Granted literature
- US20130313623A1 THRESHOLD GATE AND THRESHOLD LOGIC ARRAY Public/Granted day:2013-11-28
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