Invention Grant
US09306601B2 LDPC design for high parallelism, low error floor, and simple encoding
有权
高度并行化的LDPC设计,低错误的底层和简单的编码
- Patent Title: LDPC design for high parallelism, low error floor, and simple encoding
- Patent Title (中): 高度并行化的LDPC设计,低错误的底层和简单的编码
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Application No.: US14179942Application Date: 2014-02-13
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Publication No.: US09306601B2Publication Date: 2016-04-05
- Inventor: Thomas Joseph Richardson
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Mahamedi Paradice LLP
- Main IPC: H03M13/11
- IPC: H03M13/11 ; H03M13/03 ; H03M13/00 ; H03M13/53

Abstract:
A method of data encoding is disclosed. An encoder receives a set of information bits and performs an LDPC encoding operation on the set of information bits to produce a codeword based on a matched lifted LDPC code. The matched lifted LDPC code is based on a commutative lifting group and includes a number of parity bits and a submatrix to determine values of the parity bits. An order of the lifting group (Z) corresponds with a size of the lifting. A determinant of the submatrix is a polynomial of the form: ga+(g0+gL)P, where g0 is the identity element of the group, g0=gL2k, and P is an arbitrary non-zero element of a binary group ring associated to the lifting group.
Public/Granted literature
- US20140229789A1 LDPC DESIGN FOR HIGH PARALLELISM, LOW ERROR FLOOR, AND SIMPLE ENCODING Public/Granted day:2014-08-14
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