Invention Grant
- Patent Title: Adaptive test sequence for testing integrated circuits
- Patent Title (中): 用于测试集成电路的自适应测试序列
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Application No.: US13072325Application Date: 2011-03-25
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Publication No.: US09310437B2Publication Date: 2016-04-12
- Inventor: Chun-Cheng Chen , Hung-Chih Lin , Mill-Jer Wang , Hao Chen , Ching-Nen Peng
- Applicant: Chun-Cheng Chen , Hung-Chih Lin , Mill-Jer Wang , Hao Chen , Ching-Nen Peng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/319 ; G01R31/3183 ; G01R31/3185

Abstract:
A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence.
Public/Granted literature
- US20120246514A1 Adaptive Test Sequence for Testing Integrated Circuits Public/Granted day:2012-09-27
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