Invention Grant
- Patent Title: GOA circuit structure
- Patent Title (中): GOA电路结构
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Application No.: US14347586Application Date: 2014-01-21
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Publication No.: US09311880B2Publication Date: 2016-04-12
- Inventor: Chao Dai
- Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicant Address: CN Shenzhen, Guangdong
- Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
- Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
- Current Assignee Address: CN Shenzhen, Guangdong
- Agent Andrew C. Cheng
- Priority: CN201310746276 20131230
- International Application: PCT/CN2014/070940 WO 20140121
- International Announcement: WO2015/100813 WO 20150709
- Main IPC: G09G3/36
- IPC: G09G3/36 ; G11C19/28

Abstract:
A GOA circuit structure comprises multiple twined GOA units cascaded with each other, each said twined GOA unit comprises the (2N−1)-level GOA unit and the 2N-level GOA unit, which has a first pull-down holding circuit, a second pull-down holding circuit, a third pull-down holding circuit, and a fourth pull-down holding circuit connected with the (2N−1)-level gate signal point (Q(2N−1)) and the 2N-level gate signal point (Q(2N)). By inputting the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to make the four pull-down holding circuits work alternately. The GOA circuit structure makes each portion work for ¼ time and take rest for ¾ time by sharing the pull-down holding circuit, to reduce the TFT stress of the pull-down holding circuit.
Public/Granted literature
- US20150187312A1 GOA Circuit Structure Public/Granted day:2015-07-02
Information query
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