Invention Grant
- Patent Title: Nonvolatile semiconductor memory device and method for manufacturing same
- Patent Title (中): 非易失性半导体存储器件及其制造方法
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Application No.: US14150504Application Date: 2014-01-08
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Publication No.: US09312134B2Publication Date: 2016-04-12
- Inventor: Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2009-072950 20090324
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L21/223 ; H01L27/115 ; H01L29/66 ; H01L21/265 ; H01L29/78

Abstract:
A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
Public/Granted literature
- US09147575B2 Nonvolatile semiconductor memory device and method for manufacturing same Public/Granted day:2015-09-29
Information query
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