Invention Grant
- Patent Title: Cascoded comparator with dynamic biasing for column parallel single slope ADCs
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Application No.: US14570739Application Date: 2014-12-15
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Publication No.: US09312841B2Publication Date: 2016-04-12
- Inventor: Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Main IPC: H03D1/00
- IPC: H03D1/00 ; H03K5/00 ; H03K5/24 ; H03F3/45 ; H03M1/36 ; H03M1/12 ; H03M1/56

Abstract:
Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.
Public/Granted literature
- US20150097596A1 CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS Public/Granted day:2015-04-09
Information query
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