Invention Grant
US09312868B2 Clock phase adjusting circuit and semiconductor device including the same
有权
时钟相位调整电路及包括其的半导体器件
- Patent Title: Clock phase adjusting circuit and semiconductor device including the same
- Patent Title (中): 时钟相位调整电路及包括其的半导体器件
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Application No.: US14075703Application Date: 2013-11-08
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Publication No.: US09312868B2Publication Date: 2016-04-12
- Inventor: Dae-Suk Kim
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2013-0069550 20130618
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/197

Abstract:
A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (DLL) suitable for delaying the clock to generate a delay locked clock, a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two, a delay unit suitable for delaying the clock corrected by the DLL by a value corresponding to the digital code to output a delayed clock, and a strobing unit suitable for strobing the input signal using the delayed clock.
Public/Granted literature
- US20140368243A1 CLOCK PHASE ADJUSTING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME Public/Granted day:2014-12-18
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