Invention Grant
- Patent Title: Patterning process method for semiconductor devices
- Patent Title (中): 半导体器件的图案化处理方法
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Application No.: US14141042Application Date: 2013-12-26
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Publication No.: US09318330B2Publication Date: 2016-04-19
- Inventor: Masayoshi Tagami , Naoya Inoue
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Main IPC: H01L21/027
- IPC: H01L21/027 ; H01L21/033 ; H01L21/311 ; H01L21/768

Abstract:
A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask.
Public/Granted literature
- US20140187047A1 PATTERNING PROCESS METHOD FOR SEMICONDUCTOR DEVICES Public/Granted day:2014-07-03
Information query
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