Invention Grant
US09318501B2 Methods and structures for split gate memory cell scaling with merged control gates
有权
具有合并控制门的分离栅极存储单元缩放的方法和结构
- Patent Title: Methods and structures for split gate memory cell scaling with merged control gates
- Patent Title (中): 具有合并控制门的分离栅极存储单元缩放的方法和结构
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Application No.: US14303290Application Date: 2014-06-12
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Publication No.: US09318501B2Publication Date: 2016-04-19
- Inventor: Anirban Roy , Ko-Min Chang
- Applicant: Anirban Roy , Ko-Min Chang
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/28 ; H01L29/423 ; H01L29/66
Abstract:
A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.
Public/Granted literature
- US20150364478A1 METHODS AND STRUCTURES FOR SPLIT GATE MEMORY CELL SCALING WITH MERGED CONTROL GATES Public/Granted day:2015-12-17
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