Invention Grant
US09318568B2 Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
有权
集成非易失性存储器（NVM）单元和逻辑晶体管及其方法
- Patent Title: Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
- Patent Title (中): 集成非易失性存储器（NVM）单元和逻辑晶体管及其方法
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Application No.: US14491551Application Date: 2014-09-19
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Publication No.: US09318568B2Publication Date: 2016-04-19
- Inventor: Asanga H. Perera , Sung-Taeg Kang
- Applicant: Asanga H. Perera , Sung-Taeg Kang
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/423 ; H01L27/115 ; H01L21/3213 ; H01L21/321 ; H01L29/40 ; H01L29/66
Abstract:
A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.
Public/Granted literature
- US20160087058A1 INTEGRATION OF A NON-VOLATILE MEMORY (NVM) CELL AND A LOGIC TRANSISTOR AND METHOD THEREFOR Public/Granted day:2016-03-24
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