Invention Grant
- Patent Title: Method of manufacturing an interlayer connection substrate
- Patent Title (中): 制造层间连接基板的方法
-
Application No.: US14287242Application Date: 2014-05-27
-
Publication No.: US09320154B2Publication Date: 2016-04-19
- Inventor: Akira Soeda , Chiko Yorita , Shinichirou Tooya , Takayuki Ono , Mitsuru Takahira , Yuuichi Sekino , Akira Goto , Yoshimasa Tashiro , Hiroyuki Doi , Tsutomu Sakamoto
- Applicant: HITACHI, LTD.
- Applicant Address: JP Tokyo
- Assignee: HITACHI, LTD.
- Current Assignee: HITACHI, LTD.
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2013-111786 20130528
- Main IPC: H05K3/20
- IPC: H05K3/20 ; H05K3/46 ; H05K1/11 ; H05K3/00 ; H05K3/30

Abstract:
An electrode connected to a TH pad requiring electric conduction is formed on a bonded surface of a first multilayer substrate having piercing TH to form a solder bump on the electrode. An electrode connected to the TH pad is formed on a bonded surface of a second multilayer substrate to be bonded having a piercing TH at a position opposite the electrode formed on the first multilayer substrate to form a solder bump on the electrode. A three-layered sheet is formed by applying an adhesive as a resin material that is not completely cured to both surfaces of a core material as the cured resin, and has holes at positions corresponding to the TH and the solder bump, respectively. The first and the second multilayer substrates are then laminated having the bonded surfaces facing each other while having the three-layered sheet positioned and interposed therebetween, and batch thermocompression bonded.
Public/Granted literature
- US20140353018A1 INTERLAYER CONNECTION SUBSTRATE AND ITS MANUFACTURING METHOD Public/Granted day:2014-12-04
Information query