Invention Grant
- Patent Title: Method of manufacturing a component-embedded substrate
- Patent Title (中): 制造部件嵌入式基板的方法
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Application No.: US13824437Application Date: 2010-10-01
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Publication No.: US09320185B2Publication Date: 2016-04-19
- Inventor: Yoshio Imamura , Tohru Matsumoto , Ryoichi Shimizu
- Applicant: Yoshio Imamura , Tohru Matsumoto , Ryoichi Shimizu
- Applicant Address: JP Ayase-Shi, Kanagawa
- Assignee: MEIKO ELECTRONICS CO., LTD.
- Current Assignee: MEIKO ELECTRONICS CO., LTD.
- Current Assignee Address: JP Ayase-Shi, Kanagawa
- Agency: Marshall, Gerstein & Borun LLP
- International Application: PCT/JP2010/067259 WO 20101001
- International Announcement: WO2012/042667 WO 20120405
- Main IPC: H05K13/00
- IPC: H05K13/00 ; H05K1/02 ; H05K1/18 ; H05K1/16

Abstract:
A thin conductive layer which is to form a conductor pattern (18) is prepared, a mask layer (3) is formed on the conductive layer except a plurality of actual connection spots and at least one dummy connection spot on the conductive layer, actual solder pads (6) and a dummy solder pad (7) are formed, with use of solder, on the actual connection spots and the dummy connection spot, respectively, where the conductive layer is exposed, connection terminals (9) of an electric or electronic component (8) are connected to the actual solder pads (6), an insulating base (16) of resin is formed which is laminated directly on or indirectly via the mask layer (3) on the conductive layer and in which the component (8) is embedded, and part of the conductive layer is removed by using the dummy solder pad (7) as a reference, to form the conductor pattern (18).
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