Invention Grant
US09322876B2 Control test point for timing stability during scan capture 有权
扫描捕获期间的时序稳定性的控制测试点

Control test point for timing stability during scan capture
Abstract:
A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.
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