Invention Grant
- Patent Title: Control test point for timing stability during scan capture
- Patent Title (中): 扫描捕获期间的时序稳定性的控制测试点
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Application No.: US14826423Application Date: 2015-08-14
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Publication No.: US09322876B2Publication Date: 2016-04-26
- Inventor: Purushotam Bheemanna , Raghu G. GopalaKrishnaSetty , Pavan K. Guntipalli
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Nicholas D. Bowman; Steven Meyers
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/3185

Abstract:
A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.
Public/Granted literature
- US20150346281A1 CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE Public/Granted day:2015-12-03
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