Invention Grant
- Patent Title: Multi-level hierarchical routing matrices for pattern-recognition processors
- Patent Title (中): 用于模式识别处理器的多级分层路由矩阵
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Application No.: US12638759Application Date: 2009-12-15
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Publication No.: US09323994B2Publication Date: 2016-04-26
- Inventor: Harold B Noyes , David R. Brown
- Applicant: Harold B Noyes , David R. Brown
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G06F9/02
- IPC: G06F9/02 ; G06F13/00 ; G06F19/24 ; G06K9/00 ; G06F17/30
Abstract:
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
Public/Granted literature
- US20110145544A1 MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS Public/Granted day:2011-06-16
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