Invention Grant
- Patent Title: Tooling for coupling multiple electronic chips
- Patent Title (中): 用于耦合多个电子芯片的工具
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Application No.: US11693984Application Date: 2007-03-30
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Publication No.: US09324629B2Publication Date: 2016-04-26
- Inventor: Roger Dugas , John Trezza
- Applicant: Roger Dugas , John Trezza
- Applicant Address: US DE Wilmington
- Assignee: CUFER ASSET LTD. L.L.C.
- Current Assignee: CUFER ASSET LTD. L.L.C.
- Current Assignee Address: US DE Wilmington
- Main IPC: B44C1/165
- IPC: B44C1/165 ; B29C65/00 ; H01L23/427 ; H01L21/48 ; H01L21/683 ; H01L21/768 ; H01L23/48 ; H01L23/498 ; H01L23/538 ; H01L23/552 ; H01L23/66 ; H01L23/00 ; H01L25/065 ; H01L25/18 ; H01L25/00 ; H01S5/042 ; H01L23/488 ; H01S5/022 ; H01S5/183

Abstract:
A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
Public/Granted literature
- US20070172987A1 MEMBRANE-BASED CHIP TOOLING Public/Granted day:2007-07-26
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