Invention Grant
US09324633B2 Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for manufacturing the same 有权
具有与每个级别的芯片载体相连的导电通孔的多级封装组件及其制造方法

Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for manufacturing the same
Abstract:
A package assembly and a method for manufacturing the same are disclosed. The package assembly includes semiconductor chips, encapsulant layers, and a chip carrier. The plurality of semiconductor chips are stacked in a plurality of levels, including a lowermost level and at least one upper level. The plurality of encapsulant layers cover respective levels of semiconductor chips. The chip carrier is used for mounting lowermost-level semiconductor chips. At least one upper-level semiconductor chips are electrically coupled to the chip carrier by conductive traces. The conductive traces include extension conductors on a surface of a lower-level encapsulant layer and conductive vias which penetrate the lower-level encapsulant layer and are exposed at a bottom surface of the package assembly. The package assembly has improved high-frequency performance while having a small size and supporting multifunctionality.
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