Invention Grant
- Patent Title: Triple stack semiconductor package
- Patent Title (中): 三重堆叠半导体封装
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Application No.: US14532743Application Date: 2014-11-04
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Publication No.: US09324640B1Publication Date: 2016-04-26
- Inventor: Lee Han Meng @ Eugene Lee , Anis Fauzi Bin Abdul Aziz , Sueann Lim Wei Fen
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; Frank D. Cimino
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L25/07

Abstract:
A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.
Public/Granted literature
- US20160126230A1 TRIPLE STACK SEMICONDUCTOR PACKAGE Public/Granted day:2016-05-05
Information query
IPC分类: