Invention Grant
US09324672B2 Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
有权
半导体器件和在扇出晶片级芯片级封装中形成双主动半导体裸片的方法
- Patent Title: Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
- Patent Title (中): 半导体器件和在扇出晶片级芯片级封装中形成双主动半导体裸片的方法
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Application No.: US12545390Application Date: 2009-08-21
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Publication No.: US09324672B2Publication Date: 2016-04-26
- Inventor: Reza A. Pagaila
- Applicant: Reza A. Pagaila
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00

Abstract:
In a semiconductor device, a plurality of conductive pillars is formed over a temporary carrier. A dual-active sided semiconductor die is mounted over the carrier between the conductive pillars. The semiconductor die has first and second opposing active surfaces with first contact pads on the first active surface and second contact pads on the second active surface. An encapsulant is deposited over the semiconductor die and temporary carrier. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure is electrically connected to the conductive pillars and first contact pads of the dual-active sided semiconductor die. The temporary carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive pillars and second contact pads of the dual-active sided semiconductor die.
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