Self-aligned gate contact structure

Invention Grant

US09324709B2 Self-aligned gate contact structure 有权

Title translation: 自对准门接触结构

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Patent Title: Self-aligned gate contact structure
Patent Title (中): 自对准门接触结构
Application No.: US13969764

Application Date: 2013-08-19
Publication No.: US09324709B2

Publication Date: 2016-04-26
Inventor: Veeraraghavan S. Basker , Kangguo Cheng , Ali Khakifirooz , Viraj Y. Sardesai , Raghavasimhan Sreenivasan
Applicant: GLOBAL FOUNDRIES U.S. 2 LLC
Applicant Address: US KY Grand Cayman
Assignee: GLOBALFOUNDRIES Inc.
Current Assignee: GLOBALFOUNDRIES Inc.
Current Assignee Address: US KY Grand Cayman
Agency: Hoffman Warnick LLC
Agent Yuanmin Cai
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L27/088 ; H01L29/66 ; H01L29/49 ; H01L29/78

Abstract:

Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source/drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided.

Abstract(Chinese):

本发明的实施例提供一种形成半导体器件的方法。该方法包括在衬底中的相应一个或多个晶体管的一个或多个沟道区上沉积一层金属，该金属层具有第一区和第二区; 降低金属层的第一区域的高度; 在低高度的第一区域上形成绝缘层，所述绝缘层形成为具有与所述金属层的第二区域共面的顶表面; 以及形成至少一个接触件到所述一个或多个晶体管的源极/漏极区域。还提供了由此形成的半导体器件的结构。

Public/Granted literature

US20150048455A1 SELF-ALIGNED GATE CONTACT STRUCTURE Public/Granted day:2015-02-19

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺