Invention Grant
US09324760B2 CMOS integrated method for fabrication of thermopile pixel on semiconductor substrate with buried insulation regions
有权
CMOS集成方法,用于在具有掩埋绝缘区域的半导体衬底上制造热电堆像素
- Patent Title: CMOS integrated method for fabrication of thermopile pixel on semiconductor substrate with buried insulation regions
- Patent Title (中): CMOS集成方法,用于在具有掩埋绝缘区域的半导体衬底上制造热电堆像素
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Application No.: US14159762Application Date: 2014-01-21
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Publication No.: US09324760B2Publication Date: 2016-04-26
- Inventor: Philippe Vasseur , Grigore D. Huminic , Hermann Karagoezoglu , Radu M. Marinescu
- Applicant: Excelitas Technologies Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: Excelitas Technologies Singapore Pte. Ltd
- Current Assignee: Excelitas Technologies Singapore Pte. Ltd
- Current Assignee Address: SG Singapore
- Agency: Sheehan Phinney Bass & Green PA
- Agent Peter A. Nieves
- Main IPC: H01L27/146
- IPC: H01L27/146 ; G01J5/02 ; G01J5/12 ; H01L21/76 ; H01L31/0236

Abstract:
A method for manufacturing an imaging device in a semiconductor substrate is disclosed. The substrate includes a first surface, a second surface substantially opposite the first surface, and a thickness defined by a distance between the first surface and the second surface. A trench is fabricated in the semiconductor substrate first surface. A passivation layer is applied over the substrate first surface and the trench, optionally filling the trench by depositing a conformal layer over the substrate first surface. The conformal layer and the passivation layer are planarized from the substrate first surface, and a membrane is fabricated on the substrate first surface. From the substrate second surface, a cavity is formed in the substrate abutting the membrane and at least a portion of the trench via the unmasked region.
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