Invention Grant
- Patent Title: Self-aligned dual-height isolation for bulk FinFET
- Patent Title (中): 用于散装FinFET的自对准双高度隔离
-
Application No.: US14083571Application Date: 2013-11-19
-
Publication No.: US09324790B2Publication Date: 2016-04-26
- Inventor: Murat Kerem Akarvardar , Steven John Bentley , Kangguo Cheng , Bruce B. Doris , Jody Fronheiser , Ajey Poovannummoottil Jacob , Ali Khakifirooz , Toshiharu Nagumo
- Applicant: International Business Machines Corporation , GLOBALFOUNDRIES Inc. , Renesas Electronics Corporation
- Applicant Address: US NY Armonk JP Tokyo KY Grand Cayman
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,RENESAS ELECTRONICS CORPORATION,GLOBALFOUNDRIES INC.
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,RENESAS ELECTRONICS CORPORATION,GLOBALFOUNDRIES INC.
- Current Assignee Address: US NY Armonk JP Tokyo KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Steven J. Meyers
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L27/088 ; H01L29/06 ; H01L21/8234 ; H01L29/78 ; H01L27/092

Abstract:
A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
Public/Granted literature
- US20150137308A1 SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET Public/Granted day:2015-05-21
Information query
IPC分类: