Invention Grant
US09329227B2 Method and apparatus for testing interconnection reliability of a ball grid array on a testing printed circuit board 有权
测试印刷电路板上球栅阵列互连可靠性的方法和装置

  • Patent Title: Method and apparatus for testing interconnection reliability of a ball grid array on a testing printed circuit board
  • Patent Title (中): 测试印刷电路板上球栅阵列互连可靠性的方法和装置
  • Application No.: US13659425
    Application Date: 2012-10-24
  • Publication No.: US09329227B2
    Publication Date: 2016-05-03
  • Inventor: Dongji XieMin Woo
  • Applicant: Nvidia Corporation
  • Applicant Address: US CA Santa Clara
  • Assignee: Nvidia Corporation
  • Current Assignee: Nvidia Corporation
  • Current Assignee Address: US CA Santa Clara
  • Main IPC: G01R31/26
  • IPC: G01R31/26 G01R31/28 G01R1/04 G01R31/04
Method and apparatus for testing interconnection reliability of a ball grid array on a testing printed circuit board
Abstract:
An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented.
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