Invention Grant
US09329235B2 Localizing fault flop in circuit by using modified test pattern
有权
通过使用修改的测试图案来定位电路中的故障翻转
- Patent Title: Localizing fault flop in circuit by using modified test pattern
- Patent Title (中): 通过使用修改的测试图案来定位电路中的故障翻转
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Application No.: US14207070Application Date: 2014-03-12
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Publication No.: US09329235B2Publication Date: 2016-05-03
- Inventor: Parthajit Bhattacharya , Rohit Kapur
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Priority: IN1068/CHE/2013 20130313
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/3185 ; G01R31/3183 ; G01R31/3181 ; G01R31/319
Abstract:
A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated.
Public/Granted literature
- US20140281777A1 Localizing Fault Flop in Circuit by Using Modified Test Pattern Public/Granted day:2014-09-18
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