Invention Grant
- Patent Title: Power-efficient inter processor communication scheduling
- Patent Title (中): 高效的处理器间通信调度
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Application No.: US13753174Application Date: 2013-01-29
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Publication No.: US09329671B2Publication Date: 2016-05-03
- Inventor: Greg Heinrich , Philippe Guasch
- Applicant: Nvidia Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Nvidia Corporation
- Current Assignee: Nvidia Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F1/26
- IPC: G06F1/26 ; G06F1/32 ; G06F9/48

Abstract:
Computer system, method and computer program product for scheduling IPC activities are disclosed. In one embodiment, the computer system includes first processor and second processors that communicate with each other via IPC activities. The second processor may operate in a first mode in which the second processor is able to process IPC activities, or a second mode in which the second processor does not process IPC activities. Processing apparatus associated with the first processor identifies which of the pending IPC activities for communicating from the first processor to the second processor are not real-time sensitive, and schedules the identified IPC activities for communicating from the first processor to the second processor by delaying some of the identified IPC activities to thereby group them together. The grouped IPC activities are scheduled for communicating to the second processor during a period in which the second processor is continuously in the first mode.
Public/Granted literature
- US20140215236A1 POWER-EFFICIENT INTER PROCESSOR COMMUNICATION SCHEDULING Public/Granted day:2014-07-31
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